1. Field of the Invention
The present invention relates to a class AB operational amplifier having high gain and low settling time.
2. Description of the Related Art
As is known, speed and accuracy are requirements of primary importance in a great number of analogue electronic circuits, but the optimization of both is difficult, as contrasting needs must be satisfied. In fact, in application such as, for example, switched capacitors circuits, samplers and analogue-to-digital converters of algorithmic, sigma-delta or pipeline type, speed and accuracy depend on the behavior in transient state of the operational amplifiers. In particular, speed requires both a high cutoff frequency and substantially a single pole behavior, whereas it is necessary to increase the DC gain to improve accuracy. The need to raise the cutoff frequency leads to design single-stage amplifiers, preferably implemented with short channel MOS transistors with high bias currents; on the contrary, to obtain a high DC gain it is preferable to use multistage amplifiers, having long channel MOS transistor with low bias currents.
A number of solutions have been proposed to overcome these problems, such as the use of double or triple xe2x80x9ccascodexe2x80x9d stages, for example. However, although the double xe2x80x9ccascodexe2x80x9d stages do not impair high frequency performances, they do not allow sufficiently high DC gain values to be reached; triple xe2x80x9ccascodexe2x80x9d stages, on the other hand, allow a satisfactory gain to be obtained, but they considerably limit both the phase margin and the output dynamics of the operational amplifiers, so they can be used only in a limited field of applications.
Alternatively, transconductance stages can be dynamically biased, by reducing the bias currents according to time. In this case, however, the settling is very slow, so that these circuits are not suitable for use in high frequency applications.
A third solution has been proposed in xe2x80x9cA Fast Settling CMOS Op Amp for SC Circuits with 90-dB DC Gainxe2x80x9d, by K. Bult and G. J. G. M. Geelen, IEEE Journal of Solid-State circuitsxe2x80x9d, Vol. 25, N. 6, pages 1379-1384. In this case, in a xe2x80x9ccascodexe2x80x9d stage, gain raising stages are used to increase the overall gain of the operational amplifier up to quite high levels (about 90 dB), guaranteeing a high cutoff frequency. However, a drawback of this solution is that a pole-zero doublet is added in the operational amplifier bandwidth. As is known, the time constant of the pole-zero doublet must be lower than the dominant time constant, which determines the cutoff frequency, otherwise the frequency performances may be significantly deteriorated. This limitation is disadvantageous especially when the circuit comprises numerous operational amplifiers, having different working conditions (for example different capacitive and/or resistive loads). In this case, in fact, in order to ensure that in each operational amplifier the time constant of the pole-zero doublet is smaller than the respective dominant time constant, conditions must be imposed which may cause the settling times of the operational amplifiers themselves not to be uniform. Consequently, non linear phenomena may occur which, for example in the case of analogue-to-digital converters of sigma-delta type, can adversely affect the accuracy of the whole device.
The present invention provides an operational amplifier having improved gain with respect to frequency and improved response time with respect to input stimulus.
According to an embodiment of the present invention a class AB operational amplifier having high gain and low settling time is provided by an amplification branch; an input transistor; an output transistor having a source terminal connected to the input transistor and a drain terminal connected to a first output terminal; and a gain raising stage having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor; wherein the gain raising stage includes at least one compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.